Search - verilog sinusoidal

[VHDL-FPGA-Verilog] sinewave

Description: 6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
Platform: | Size: 1024 | Author: 桑武斌 | Hits:

[VHDL-FPGA-Verilog] oneperiod

Description: 将正弦波分割，数字化处理，即dds技术，为verilog做准备-Will be sinusoidal segmentation, digital processing, that is, dds technology, ready to do for the Verilog
Platform: | Size: 3072 | Author: 严新文 | Hits:

[Other Embeded program] verilog_sin_complete

Description: verilog设计正弦波波形模块,可自己通过参数设置得到所需峰值的波形-Verilog design module sinusoidal waveform can be themselves through the necessary parameters of the waveform peak
Platform: | Size: 3072 | Author: 刘彬 | Hits:

[VHDL-FPGA-Verilog] sine

Description: Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Platform: | Size: 2529280 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[VHDL-FPGA-Verilog] FPGAdezizhixingSPWMboChengXu

Description: 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!
Platform: | Size: 4096 | Author: 小喻 | Hits:

[VHDL-FPGA-Verilog] SPWM

Description: VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
Platform: | Size: 7168 | Author: zyb | Hits:

[Graph Drawing] dds(heli)

Description: DDS用verilog 实现，可以实现方波、正弦和三角-DDS using verilog realized, can be square wave, sinusoidal and triangular
Platform: | Size: 428032 | Author: qian | Hits:

[VHDL-FPGA-Verilog] sin

Description: QUARTUSS||环境下的简易正弦信号发生器的设计，VERILOG 代码，用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
Platform: | Size: 2955264 | Author: sujiebin | Hits:

[VHDL-FPGA-Verilog] ad9850

Description: AD9850的控制程序，用于产生各种频率的正弦信号-AD9850 control program, used to generate sinusoidal signals of various frequencies
Platform: | Size: 1024 | Author: godspeed | Hits:

[VHDL-FPGA-Verilog] sixiangzaibosheji

Description: 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70MHz output frequency of the four four-phase sequence of a sinusoidal carrier (phase were 0 °, 90 °, 180 °, 270 °) design. Using Verilog HDL language for the programming and design with the Quartus Ⅱ of the simulation to verify its correctness.
Platform: | Size: 5120 | Author: biyuming | Hits:

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[VHDL-FPGA-Verilog] sinewave

[VHDL-FPGA-Verilog] oneperiod

[Other Embeded program] verilog_sin_complete

[VHDL-FPGA-Verilog] sine

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] rom

[Software Engineering] DDS

[VHDL-FPGA-Verilog] FPGAdezizhixingSPWMboChengXu

[VHDL-FPGA-Verilog] SPWM

[Graph Drawing] dds(heli)

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] ad9850

[VHDL-FPGA-Verilog] sixiangzaibosheji

[VHDL-FPGA-Verilog] sine

[VHDL-FPGA-Verilog] 06-NEC_2005_A

[Program doc] mysunrom

[VHDL-FPGA-Verilog] edasingene

[VHDL-FPGA-Verilog] sinewave-case

[VHDL-FPGA-Verilog] singnt

[VHDL-FPGA-Verilog] test_ADDA_sin

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